1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device for improving element characteristics by improvement of the structure of a transistor and a method of manufacturing thereof.
2. Description of the Background Art
A VLSI (Very Large Scale Integrated Circuit) represented by a memory and a processor tends to be made large in scale recently. In order to meet with this requirement for a larger scale, a CMOS having features of high integration density and low power consumption has become the mainstream. However, such is the state that requirement for a higher speed is not sufficiently met even though an operating speed of a MOS has been enhanced because of progress of a miniaturization technique. From the view point of high speed, bipolar implementation centered at ECL (Emitter Coupled Logic) is usually the mainstream. However, power consumption of a bipolar device is extremely high, which imposes a great limit on high integration density.
Under these circumstances, in order to implement a device operable at a high speed with low power consumption, much attention has been paid to a Bi-CMOS transistor which can have CMOS's features of high integration density and low power consumption, and a bipolar implementation's feature of a high speed.
Referring to FIG. 15, a Bi-CMOS transistor 900 is often used in a peripheral circuit as a transistor for driving a memory cell 551 provided in a semiconductor device 550. An equivalent circuit of the Bi-CMOS transistor 900 is shown in FIG. 16.
A structure of the above-described Bi-CMOS transistor 900 is described in, for example, Japanese Patent Laying-Open No. 62-219554 and the like.
Referring to FIG. 17, an n.sup.- type epitaxial layer 502 is formed on a p.sup.- type semiconductor substrate of single crystal silicon.
An n.sup.+ type buried layer 503A of high concentration is formed extending over the semiconductor substrate 501 and the epitaxial layer 502 in a region where a bipolar transistor 600 is to be formed.
An n.sup.+ type buried layer 503B of high concentration is formed extending over the semiconductor substrate 501 and the epitaxial layer 502 in a region where a p channel MOS type field effect transistor 700 is to be formed.
The bipolar transistor 600 of the Bi-CMOS transistor 900 includes, as shown on the left side of FIG. 17, the n.sup.+ buried layer 503A, an n.sup.+ collector wall 507 of high concentration, the epitaxial layer 502, a p.sup.- base region 508, and an n.sup.+ emitter region 511 B of high concentration. The collector region includes the buried layer 503A, the collector wall 507 and the epitaxial layer 502. The collector wall 507 is connected to an electrode 515 for the collector wall through a connection hole 514 provided at an interlayer insulating layer 513. The base region 508 is electrically connected to the electrode 515 for base through the connection hole 514. The n.sup.+ emitter 511B is electrically connected to an emitter electrode 510B through a connection hole (with no reference numeral allotted) provided at a gate oxide film 509.
The p channel MOS type field effect transistor 700 of the Bi-CMOS transistor 900 includes, as shown in the center of FIG. 17, an n well of the n.sup.+ buried layer 503B, the n.sup.- epitaxial layer 502, the gate oxide film 509, a gate electrode 510A, and a pair of p.sup.+ source and p.sup.+ drain regions 512 of high concentration.
The n type well region has the bottom portion formed of the n.sup.+ buried layer 503B of high concentration. The n.sup.+ buried layer 503B is implemented to reduce the current amplifying rate of a parasitic bipolar transistor having the above-described well region as a base region to prevent a so-called latch up phenomenon of the parasitic bipolar transistor.
The p.sup.+ source region/p.sup.+ drain region 512 is electrically connected to the electrode 515 for source or drain through the connection hole 514.
Latch up is a phenomenon where pnp type and npn type parasitic bipolar transistors in a CMOS transistor implement a pnpn thyristor between power supply potential (V.sub.DD) and ground potential GND (V.sub.SS) in which an externally applied noise will cause continuous current flow between V.sub.DD and GND to induce breakdown of the CMOS transistor.
FIG. 18 is a sectional view schematically showing an example of a parasitic thyristor formed in the CMOS transistor of FIG. 17. If the impurity concentration of the n well 502 and the p well 506 is low in the CMOS transistor, the application of some surge noise will increase the voltage effect (voltage effect corresponding to resistors Rn and Rp) when current flows to these well regions. As a result, the parasitic pnp bipolar transistor Q1 and the parasitic npn bipolar transistor Q2 have their emitters and bases biased. The operation of these parasitic transistors will increase the possibility of the above-described latch up phenomenon.
An n channel MOS field effect transistor 800 of the Bi-CMOS transistor 900 includes, as shown on the right side of FIG. 17, a p.sup.+ buried layer 505A of high concentration, a p well 506 of low concentration, the gate oxide film 509, the gate electrode 510A, and n.sup.+ source region and n.sup.+ drain region 511A of high concentration. The p well 506 has its bottom portion formed of the p.sup.+ buried layer 505A of high concentration as well as the above-described n well. The p.sup.+ buried layer 505A is implemented to prevent the latch up phenomenon as well as the above.
The n.sup.+ source region and n.sup.+ drain region 511A is electrically connected to the electrode 515 for source or drain through the connection hole 514.
An isolation region is provided between the respective forming regions of the bipolar transistor 600, the p channel MOS type field effect transistor 700, and the n channel MOS type field effect transistor 800 which implement the above-described Bi-CMOS transistor 900.
The isolation region is formed of an isolation oxide film 504 provided on the main surface of the n.sup.- epitaxial layer 502, and a semiconductor region 505B for p.sup.+ isolation of high concentration contacting the bottom face of the isolation oxide film 504 and provided on the main surface of the n.sup.- epitaxial layer 502 at a position higher than that of the p.sup.+ buried layer 505A.
A method of manufacturing the above-described Bi-CMOS transistor 900 will now be described. FIGS. 19-21 are cross-sectional views of the Bi-CMOS transistor 900 in respective steps of the manufacturing process thereof in accordance with the cross-sectional structure shown in FIG. 17.
Referring to FIG. 19, the n.sup.+ buried layers 503A, 503B are formed on the forming regions of the bipolar transistor 600 and the p channel MOS type field effect transistor 700, respectively, of the main surface of the p.sup.- type semiconductor substrate 501. Then, the n.sup.- type epitaxial layer 502 is stacked on the main surface of the semiconductor substrate 501. At this time, because of heat for growth of the epitaxial layer 502, impurities in the n.sup.+ buried layers 503A, 503B are diffused into the epitaxial layer.
Referring to FIG. 20, the isolation oxide film 504 is formed at a predetermined position on the main surface of the epitaxial layer 502 between the forming regions of the semiconductor elements by using a LOCOS method. Then, the gate oxide film 509 is formed on the surface of the epitaxial layer 502.
Referring to FIG. 21, the p.sup.+ buried region 505A and the semiconductor region 505B for p.sup.+ isolation are formed at the main surface portion of the epitaxial layer 502 of the forming region of the n channel MOS type field effect transistor 800, and of the forming region of the isolation region, respectively.
The p.sup.+ buried region 505A, the semiconductor region 505B for p.sup.+ isolation, and the p well 506 are formed by a predetermined ion implantation using a resist film 516 (shown by a dot dash line in the figure). Then, the n.sup.+ collector wall 507, the p.sup.- base 508 and the n.sup.+ emitter 511B are formed in order in the forming region of the bipolar transistor 600.
In the forming region of the p channel MOS type field effect transistor 700, the gate electrode 510A, and the pair of p.sup.+ source region and p.sup.+ drain region 512 are formed in order.
In the forming region of the n channel MOS type field effect transistor 800, the gate electrode 510A, and the pair of n.sup.+ source region and n.sup.+ drain region 511A are formed in order.
After further forming the interlayer insulating film 513, the connection hole 514, and the respective electrodes 515 are formed. By carrying out the series of manufacturing steps, the Bi-CMOS transistor 900 is completed.
However, in the above-described structure, since isolation of the p channel MOS type field effect transistor 700 from the n channel MOS type field effect transistor 800 is insufficient, the parasitic thyristor element is rendered conductive, causing a large current flow to be produced between power supply terminals of a CMOS circuit and the like, the circuit operation to be hampered, and the semiconductor device itself to be destroyed. This is a so-called latch up phenomenon.
Referring to FIG. 22, FIG. 22 shows concentration distribution of impurities in cross-section taken along the line I--I of FIG. 17.
In the above-described prior art, the p.sup.+ buried layer 505A and a p.sup.+ channel stop layer 505B are simultaneously formed by a single impurity implantation, and the maximum value of concentration distribution of impurities is in the region (d1 in the figure) directly beneath the isolation oxide film 504. Therefore, concentration of impurities was lower at a position of the p.sup.+ channel stop deeper in the direction of depth of the substrate, which, in turn, caused insufficient isolation resulting in the above-described latch-up phenomenon.